SCHEDULE: NOV 15-20, 2015

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Analyzing and Mitigating the Impact of Manufacturing Variability in Power-Constrained Supercomputing

SESSION: Power-Constrained Computing

EVENT TYPE: Papers

EVENT TAG(S): Power, Performance

TIME: 3:30PM - 4:00PM

SESSION CHAIR(S): Karen L. Karavanic

AUTHOR(S):Yuichi Inadomi, Tapasya Patki, Koji Inoue, Mutsumi Aoyagi, Barry Rountree, Martin Schulz, David Lowenthal, Yasutaka Wada, Keiichiro Fukazawa, Masatsugu Ueda, Masaaki Kondo, Ikuo Miyoshi

ROOM:19AB

ABSTRACT:

A key challenge in next-generation supercomputing is to effectively schedule limited power resources. Modern processors suffer from increasingly large power variations owing to the chip manufacturing process. These variations lead to power inhomogeneity in current systems and manifest into performance inhomogeneity in power constrained environments, drastically limiting supercomputing performance. We present a first-of-its-kind manufacturing variability study on four production HPC systems spanning four microarchitectures, analyze its impact on HPC applications, and propose a novel variation-aware power budgeting scheme to maximize effective application performance.
Our low-cost and scalable budgeting algorithm strives to achieve performance homogeneity under a power constraint by deriving application-specific, module-level power allocations. Experimental results using a 1,920 socket system show up to 5.4X speedup, with an average speedup of 1.8X across all benchmarks, compared to a variation-unaware power allocation scheme.

Chair/Author Details:

Karen L. Karavanic (Chair) - Portland State University|

Yuichi Inadomi - Kyushu University

Tapasya Patki - University of Arizona

Koji Inoue - Kyushu University

Mutsumi Aoyagi - Kyushu University

Barry Rountree - Lawrence Livermore National Laboratory

Martin Schulz - Lawrence Livermore National Laboratory

David Lowenthal - University of Arizona

Yasutaka Wada - Meisei University

Keiichiro Fukazawa - Kyoto University

Masatsugu Ueda - Kyushu University