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PRODID:-//Microsoft Corporation//Outlook MIMEDIR//EN
VERSION:1.0
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DTSTART:20151119T213000Z
DTEND:20151119T220000Z
LOCATION:19AB
DESCRIPTION;ENCODING=QUOTED-PRINTABLE:ABSTRACT: A key challenge in next-generation supercomputing is to effectively schedule limited power resources. Modern processors suffer from increasingly large power variations owing to the chip manufacturing process. These variations lead to power inhomogeneity in current systems and manifest into performance inhomogeneity in power constrained environments, drastically limiting supercomputing performance. We present a first-of-its-kind manufacturing variability study on four production HPC systems spanning four microarchitectures, analyze its impact on HPC applications, and propose a novel variation-aware power budgeting scheme to maximize effective application performance.=0AOur low-cost and scalable budgeting algorithm strives to achieve performance homogeneity under a power constraint by deriving application-specific, module-level power allocations. Experimental results using a 1,920 socket system show up to 5.4X speedup, with an average speedup of 1.8X across all benchmarks, compared to a variation-unaware power allocation scheme.
SUMMARY:Analyzing and Mitigating the Impact of Manufacturing Variability in Power-Constrained Supercomputing
PRIORITY:3
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